Automated Synthesis of Hardware Process Networks from Sequential C Code

In this thesis, we present a methodology for the automated generation of complete hardware implementations from C input specifications. Our methodology is based on the Kahn Process Network (KPN) Model of Computation (MoC). By leveraging previous research, we can automatically obtain a parallel KPN representation of sequential C input code. Next, we synthesize RTL implementations of the KPN nodes, by making use of PICO, a high level synthesis tool, to automatically obtain an RTL implementation of the node functionality. An important benefit of our approach is that source code annotations that indicate parallelism or influence low-level implementation decisions are not required for efficient results. This allows for an efficient software engineering design flow to program FPGAs. We show that by applying transformations to KPNs, one can obtain different application instances with improved throughput of the resulting hardware implementations. We also show that the distributed memory model inherent to the KPN MoC suits well to customizable hardware target platforms like FPGAs.